SL2S2602 datasheet(9/55 Pages) NXP

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NXP Semiconductors

SL2S2602

ICODE SLIX2

SL2S2602

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.1 — 25 July 2017

COMPANY PUBLIC

276341

9 / 55

8 Mechanical specification

The ICODE SLIX2 wafers are available in 120 μm thickness. The 120 μm thick wafer

is enhanced with 7 μm Polyimide spacer providing better assembly tolerance (e.g.

pressure).

8.1 Wafer specification

See Ref. 6 "General specification for 8" wafer on UV-tape with electronic fail die

marking".

Table 5. Wafer specification

Wafer

Designation

each wafer is enscribed with batch number and wafer number

Diameter

200 mm (8 inches)

Thickness

120 μm ± 15 μm

Process

CMOS 0.14 μm

Batch size

25 wafers

Dies per wafer

94823

Wafer backside

Material

Treatment

ground and stress release

Ra minimum = 0.5 μm

Roughness

Rt maximum = 5 μm

Chip dimensions

Die size without scribe

540 μm × 543 μm = 0.29322 mm2

Scribe line width

X-dimension

15 μm (scribe line width measured between nitride edges)

Y-dimension

15 μm (scribe line width measured between nitride edges)

Number of pads

Pad location

non-diagonal/placed in chip corners

Distance pad to pad LA to LB

430 μm (center to center)

Distance pad to pad LB to TEST

371.5 μm (center to center)

Passivation on front

Type

sandwich structure

Material

PE-nitride (on top)

Thickness

1.75 μm total thickness of passivation

Polyimide spacer

7 μm ± 1 μm

Au bump

Material

>99.9 % pure Au

Hardness

35 HV to 80 HV 0.005

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