M95M04-DR datasheet(19/46 Pages) STMICROELECTRONICS

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DS12179 Rev 1

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M95M04-DR

Instructions

6.3

Read Status register (RDSR)

The Read Status register (RDSR) instruction is used to read the Status register. The Status

progress. When one of these cycles is in progress, it is recommended to check the Write in

progress (WIP) bit before sending a new instruction to the device. It is also possible to read

the Status register continuously, as shown in Figure 10.

Figure 10. Read Status register (RDSR) sequence

The status and control bits of the Status register are detailed in the following subsections.

6.3.1

WIP bit

The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the

device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a

Write cycle (tW) is in progress, the device is busy and the WIP bit is set to 1. When WIP = 0

the device is ready to decode a new command.

During a Write cycle, reading continuously the WIP bit allows to detect when the device

becomes ready (WIP = 0) to decode a new command.

6.3.2

WEL bit

The WEL bit (Write enable latch) bit is a flag that indicates the status of the internal Write

enable latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are

executed; when WEL is set to 0, any decoded Write instruction is not executed.

The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the

following events:

•

Write disable (WRDI) instruction completion

•

Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle

time tW

•

Power-up

6.3.3

BP1, BP0 bits

The Block protect (BP1, BP0) bits are non volatile. They define the size of the area to be

software-protected against Write instructions. These bits are written with the Write Status

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