MPC852T datasheet(13/80 Pages) FREESCALE

13 / 80 page

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

supply pins. For more information, please refer to MPC866 User’s Manual, Section 14.4.3, “Clock Synthesizer

Power (VDDSYN, VSSSYN, VSSSYN1).”

12 Bus Signal Timing

The maximum bus speed that the MPC852T supports is 66 MHz. Table7 shows the frequency ranges for standard

part frequencies.

Table9 provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz.

The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum

delays. CLKOUT assumes a 100-pF load maximum delay

Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part

Freq

50MHz

66MHz

Min

Max

Min

Max

Core

Freq

66.67

Bus Freq

66.67

Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part

Freq

50MHz

66MHz

80MHz

100MHz

Min

Max

Min

Max

Min

Max

Min

Max

Core

Freq

66.67

100

Bus Freq

2:1

33.33

Table 9. Bus Operation Timings

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Bus period (CLKOUT) See Table7

—

B1a

EXTCLK to CLKOUT phase skew - If CLKOUT

is an integer multiple of EXTCLK, then the

rising edge of EXTCLK is aligned with the

rising edge of CLKOUT. For a non-integer

multiple of EXTCLK, this synchronization is

lost, and the rising edges of EXTCLK and

CLKOUT have a continuously varying phase

skew.

-2

B1b

CLKOUT frequency jitter peak-to-peak

—

B1c

Frequency jitter on EXTCLK 1

—

0.50

—

0.50

—

0.50

—

0.50%

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