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MPC852T bảng dữ liệu(PDF) 39 Page - Freescale Semiconductor, Inc

tên linh kiện MPC852T
Giải thích chi tiết về linh kiện  Hardware Specifications
PDF  80 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC852T bảng dữ liệu(HTML) 39 Page - Freescale Semiconductor, Inc

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MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconductor
39
Bus Signal Timing
Table 14 shows the reset timing for the MPC852T.
Table 14. Reset Timing
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
J82
CLKOUT to HRESET high impedance (MAX =
0.00 x B1 + 20.00)
20.00
20.00
20.00
20.00
ns
J83
CLKOUT to SRESET high impedance (MAX =
0.00 x B1 + 20.00)
20.00
20.00
20.00
20.00
ns
J84
RSTCONF pulse width (MIN = 17.00 x B1)
515.20
425.00
340.00
257.60
ns
J85
J86
Configuration data to HRESET rising edge set
up time (MIN = 15.00 x B1 + 50.00)
504.50
425.00
350.00
277.30
ns
J87
Configuration data to RSTCONF rising edge set
up time (MIN = 0.00 x B1 + 350.00)
350.00
350.00
350.00
350.00
ns
J88
Configuration data hold time after RSTCONF
negation (MIN = 0.00 x B1 + 0.00)
0.00
0.00
0.00
0.00
ns
J89
Configuration data hold time after HRESET
negation (MIN = 0.00 x B1 + 0.00)
0.00
0.00
0.00
0.00
ns
J90
HRESET and RSTCONF asserted to data out
drive (MAX = 0.00 x B1 + 25.00)
25.00
25.00
25.00
25.00
ns
J91
RSTCONF negated to data out high impedance.
(MAX = 0.00 x B1 + 25.00)
25.00
25.00
25.00
25.00
ns
J92
CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance. (MAX = 0.00 x B1 + 25.00)
25.00
25.00
25.00
25.00
ns
J93
DSDI, DSCK set up (MIN = 3.00 x B1)
90.90
75.00
60.00
45.50
ns
J94
DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00)
0.00
0.00
0.00
0.00
ns
J95
SRESET negated to CLKOUT rising edge for
DSDI and DSCK sample (MIN = 8.00 x B1)
242.40
200.00
160.00
121.20
ns



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