LS1022A datasheet(9/71 Pages) FREESCALE

9 / 71 page

TWR-LS1021A Reference Manual, Rev. 0

Freescale Semiconductor

Tables

Table

Number

Title

Page

Number

1-1

Related documentation............................................................................................................ 1-1

2-1

Processor functional blocks .................................................................................................... 2-1

2-2

Power supply overview ........................................................................................................... 2-3

2-3

Configuration options ............................................................................................................. 2-7

2-4

SYSCLK frequency options.................................................................................................... 2-8

2-5

DDRCLK frequency options .................................................................................................. 2-8

2-6

LS1021A SerDes protocols.................................................................................................. 2-10

2-7

Specific mini PCIe pinout ..................................................................................................... 2-11

2-8

SerDes configuration............................................................................................................. 2-12

2-9

Ethernet port locations .......................................................................................................... 2-13

2-10

IFC devices ........................................................................................................................... 2-16

2-11

IFC chip select mapping ....................................................................................................... 2-17

2-12

IFC 32b address mapping .....................................................................................................2-17

2-13

DIU configuration ................................................................................................................. 2-19

2-14

I2C bus device map............................................................................................................... 2-20

2-15

SPI configuration .................................................................................................................. 2-22

2-16

Interrupt connections............................................................................................................. 2-23

2-17

LPUART1 configuration.......................................................................................................2-25

2-18

GPIO mapping ...................................................................................................................... 2-26

2-19

LED status monitors.............................................................................................................. 2-27

3-1

TWR-LS1021A primary connector pinout ............................................................................. 3-1

3-2

TWR-LS1021A secondary connector pinout.......................................................................... 3-4

3-3

Supported peripheral TWR modules....................................................................................... 3-7

3-4

Signal connections between TWR-IND-IO and TWR-LS1021A........................................... 3-8

3-5

Signal connections between TWR-SER2 and TWR-LS1021A .............................................. 3-9

3-6

Signal connections between TWR-EtherCAT-SLV and TWR-LS1021A ............................... 3-9

3-7

Signal connections between TWR-MC-LV3PH and TWR-LS1021A.................................. 3-10

3-8

Signal connections between TWR-LCD and TWR-LS1021A ............................................. 3-11

3-9

Signal connections between TWR-LCD-RGB and TWR-LS1021A.................................... 3-13

4-1

CPLD memory map ................................................................................................................ 4-3

4-2

CPLD BCSR register block map ............................................................................................ 4-3

4-3

CPLD BCSR register detail map ............................................................................................ 4-4

5-1

Switch configuration ............................................................................................................... 5-3

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