FOR AUTOMOTIVE 105

°C OPERATION 2-WIRE SERIAL E

S-24CS01A/02A/04A H Series

17

7. 3 Sequential read

When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "1"

following a start condition both in current and random read operations, it responds with an acknowledge.

An 8-bit data is then sent from the S-24CS01A/02A/04A synchronous to the SCL clock and the address counter is

automatically incremented at the falling edge of the SCL clock for the 8th bit data.

When the master device responds with an acknowledge, the data at the next memory address is transmitted.

Response with an acknowledge by the master device has the memory address counter in the S-24CS01A/02A/04A

incremented and makes it possible to read data in succession. This is called "Sequential Read".

The master device outputs stop condition not an acknowledge , the reading of S-24CS01A/02A/04A is ended.

Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word

address, it rolls over to the first memory address.

R

E

A

D

S

T

O

P

DEVICE

ADDRESS

R

/

W

ADR INC

A

C

K

A

C

K

A

C

K

1

ADR INC

A

C

K

ADR INC

SDA

LINE

DATA(n)

D7

D0

D7

D0

D7

D0

D7

D0

DATA (n+1)

DATA (n+2)

DATA (n+x)

NO ACK from

Master Device

ADR INC

Figure 17 Sequential Read