FOR AUTOMOTIVE 105

°C OPERATION 2-WIRE SERIAL E

S-24CS01A/02A/04A H Series

14

6. 3 Write protect

memory area is forbidden at all.

When the WP pin is connected to the GND, the write protect is invalid, and write operation in all memory area is

available.

Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of the write

time (10 ms max.). If the WP pin changes during this time, the address data being written at this time is not

guaranteed.

There is no need for using write protect, the WP pin should be connected to the GND. The write protect is valid in the

operating voltage range.

SDA

WP

SCL

Acknowledge

WP Pin Fixed Period

Stop

Condition

Start

Condition

Write Data

D0

Figure 14 WP Pin Fixed Period

6. 4 Acknowledge polling

Acknowledge polling is used to know the completion of the write cycle in the S-24CS01A/02A/04A.

After the S-24CS01A/02A/04A receives a stop condition and once starts the write cycle, all operations are forbidden

and no response is made to the signal transmitted by the master device.

Accordingly the master device can recognize the completion of the write cycle in the S-24CS01A/02A/04A by

detecting a response from the slave device after transmitting the start condition, the device address and the read/write

instruction code to the S-24CS01A/02A/04A, namely to the slave devices.

That is, if the S-24CS01A/02A/04A does not generate an acknowledge, the write cycle is in progress and if the

S-24CS01A/02A/04A generates an acknowledge, the write cycle has been completed.

Keep the level of the WP pin fixed until acknowledge is confirmed.

It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the master device.