DP83821 datasheet(43/86 Pages) NSC

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4.0 Register Set (Continued)

MRM_DIS

Memory Read Multiple

Disable

This bit can be used to prevent the DP83821 from using the Memory Read

Multiple and Memory Read Line commands. This bit is loaded from

EEPROM at power-up. R/W

MWI_DIS

Memory Write and Invalidate

Disable

This bit can be used to prevent the DP83821 from using the MWI

command. This allows additional control for driver software which may not

have access to the MWIEN bit in Configuration space. This bit is loaded

from EEPROM at power-up. R/W

Reserved

This bit must be loaded as a 0 from the EEPROM (location 05h, bit 3) at

power-up. RO

Reserved

This bit must be a 0 for proper operation. RO

Reserved

This bit must be loaded as a 0 from the EEPROM (location 05h, bit 2) at

power-up for proper operation. R/W

Reserved

This bit must be loaded as a 0 from the EEPROM (location 05h, bit 1) at

power-up for proper operation. R/W

PHY_RST

Reset Phy

Asserts reset to phy using the PHYRST_N pin. R/W

PHY_DIS

Disable Phy

Setting this bit can be used to disable an external phy by deasserting the

RXEN pin. This can be used to cause a phy to tri-state its RX MII/GMII pins.

R/W

EXTSTS_EN Extended Status Enable

When set, the Extended Status field is enabled for Transmit and Receive

Descriptors. This field contains data for supporting the VLAN and IP

Checksum processing features. R/W

REQALG

PCI Bus Request Algorithm

Selects mode for making requests for the PCI bus. When set to 0 (default),

DP83821 will use an aggressive Request scheme. When set to a 1

DP83821 will use a more conservative scheme. R/W

Single Back-off

Setting this bit to 1, forces the transmitter back-off state machine to always

back-off for a single 802.3 interframe gap time, instead of following the

802.3 random back-off algorithm. A 0 (default) allows normal transmitter

back-off operation. R/W

POW

Program Out of Window

Timer

This bit controls when the Out of Window collision timer begins counting its

512 bit slot time. A 0 causes the timer to start after the SFD is received. A 1

causes the timer to start after the first bit of the preamble is received. R/W

EXD

Excessive Deferral Abort

Setting this bit to 1 will cause the transmitter to abort transmission on an

excessive deferral. R/W

PESEL

Parity Error Detection Action

This bit controls the assertion of SERR when a data parity error is detected

while the DP83821 is acting as the bus master. When set, parity errors will

not result in the assertion of SERR. When reset, parity errors will result in

the assertion of SERR, indicating a system error. This bit should be set to a

1 by software if the driver can handle recovery from and reporting of data

parity errors. R/W

BROM_DIS

Disable Boot ROM interface

When set to 1, this bit inhibits the operation of the Boot ROM interface

logic. R/W

EXT_125

External 125MHz reference

Select

When set to a 1, the 125MHz transmit clock for 1000 Mb/s mode is sourced

from the REF125 pin. When set to a 0, the clock is sourced by the internal

clock generator. This bit is loaded from EEPROM at power-up. R/W

BEM

Big Endian Mode

When set, DP83821 will perform bus-mastered data transfers in “big

endian” mode. Note that access to register space is unaffected by the

setting of this bit. R/W

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