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DP83821 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện DP83821
Giải thích chi tiết về linh kiện  10/100/1000 Mb/s PCI Ethernet Network Interface Controller
PDF  86 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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2.0 Pin Descriptions (Continued)
SERRN
11
I/O
System Error: This signal is asserted low by DP83821 during address parity
errors and system errors if enabled.
STOPN
9
I/O
Stop: This signal is asserted low by the target device to request the master
device to stop the current transaction.
TRDYN
6
I/O
Target Ready: As a target, this signal will be asserted low when the (slave)
device is ready to complete the current data phase transaction. This signal is
used in conjunction with the IRDYN signal. Data transaction takes place at the
rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a
master, this signal indicates that the target is ready for the data during write
operation and with the data during read operation.
PMEN
175
O
Power Management Event: This signal is asserted low by DP83821 to
indicate that a power management event has occurred.
3VAUX
86
I
PCI Aux Voltage Sense: This pin is used to sense the presence of a 3.3v
auxiliary supply in order to define the PME Support available.
This pin pad has an internal weak pull down.
PWRGOOD
85
I
PCI bus power good: Connected to PCI bus 3.3v power, this pin is used to
sense the presence of PCI bus power during the D3 power management state.
This pin pad has an internal weak pull down.
CLKRUNN
87
I/O
Clockrun: This signal is asserted low by DP83821 to indicate that a Clockrun
Event has occurred.
PCIVIO
84
I
PCI Bus VIO: This pin should be connected to the VIO pins of the PCI bus. It
provides a direct connection to the ESDPLUS ring for biasing. It may be
connected to 5V if available. It should not be connected to 3.3V unless all
signaling is 3.3V as this will interfere with 5V tolerance. Care should be taken in
connecting this to power supplies when power management functions are
enabled.
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).
Symbol
Pin No(s)
Direction
Description
COL
170
I
Collision Detect: The COL signal is asserted high asynchronously by the
external PMD upon detection of a collision on the medium. It will remain
asserted as long as the collision condition persists.
CRS/SIGDET
169
I
Carrier Sense: This signal is asserted high asynchronously by the external
physical unit upon detection of a non-idle medium.
Signal Detect: In TBI mode, this signal is used to bring in the Signal Detect
indication from the Phy.
MDC
138
O
Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used
to transfer management data for the external PMD on the MDIO pin.
MDIO
139
I/O
Management Data I/O: Bidirectional signal used to transfer management
information for the external PMD. Requires an external 4.7 K
Ω pullup resistor.
PCI Interface
Symbol
Pin No(s)
Direction
Description



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