HD64F2145 datasheet(290/829 Pages) RENESAS

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Rev. 2.0, 08/02, page 250 of 788

11.3.8

Timer Control Register (TCR)

TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer

mode, and selects the FRC clock source.

Bit

Bit Name

Initial Value

R/W

Description

IEDGA

R/W

Input Edge Select A

Selects the rising or falling edge of the input capture A

signal (FTIA).

0: Capture on the falling edge of FTIA

1: Capture on the rising edge of FTIA

IEDGB

R/W

Input Edge Select B

Selects the rising or falling edge of the input capture B

signal (FTIB).

0: Capture on the falling edge of FTIB

1: Capture on the rising edge of FTIB

IEDGC

R/W

Input Edge Select C

Selects the rising or falling edge of the input capture C

signal (FTIC).

0: Capture on the falling edge of FTIC

1: Capture on the rising edge of FTIC

IEDGD

R/W

Input Edge Select D

Selects the rising or falling edge of the input capture D

signal (FTID).

0: Capture on the falling edge of FTID

1: Capture on the rising edge of FTID

BUFEA

R/W

Buffer Enable A

Selects whether ICRC is to be used as a buffer register

for ICRA.

0: ICRC is not used as a buffer register for ICRA

1: ICRC is used as a buffer register for ICRA

BUFEB

R/W

Buffer Enable B

Selects whether ICRD is to be used as a buffer register

for ICRB.

0: ICRD is not used as a buffer register for ICRB

1: ICRD is used as a buffer register for ICRB

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