HD64F2145 datasheet(271/829 Pages) RENESAS

271 / 829 page

Rev. 2.0, 08/02, page 231 of 788

• DADRB

Bit

Bit Name

Initial Value

R/W

Description

DA13

DA12

DA11

DA10

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

R/W

D/A Data 13 to 0

These bits set a digital value to be converted to an

analog value.

In each base cycle, the DACNT value is continually

compared with the DADR value to determine the duty

cycle of the output waveform, and to decide whether to

output a fine-adjustment pulse equal in width to the

resolution. To enable this operation, this register must

be set within a range that depends on the CFS bit. If the

DADR value is outside this range, the PWM output is

held constant.

A channel can be operated with 12-bit precision by

keeping the two lowest data bits (DA1 and DA0) cleared

to 0. The two lowest data bits correspond to the two

highest bits in DACNT.

CFS

R/W

Carrier Frequency Select

0: Base cycle = resolution (T)

× 64

DADR range = H'0401 to H'FFFD

1: Base cycle = resolution (T)

× 256

DADR range = H'0103 to H'FFFF

REGS

R/W

DADRA and DACR, and DADRB and DACNT, are

located at the same addresses. The REGS bit specifies

which registers can be accessed.

0: DADRA and DADRB can be accessed

1: DACR and DACNT can be accessed

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