HD64F2145 datasheet(264/829 Pages) RENESAS

264 / 829 page

Rev. 2.0, 08/02, page 224 of 788

• PWOERB

Bit

Bit Name

Initial Value

R/W

Description

OE15

OE14

OE13

OE12

OE11

OE10

OE9

OE8

R/W

Output Enable 15 to 8

These bits, together with P2DDR, specify the P2n/PWn

pin state. Bits OE15 to OE8 correspond to outputs

PW15 to PW8.

P2nDDR OEn: Pin state

0X: Port input

10: Port output or PWM 256/256 output

11: PWM output (0 to 255/256 output)

Legend

Don't care

To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set

to port output. The corresponding pin can be set as port output in single-chip mode or when IOSE

= 1 and CS256E = 0 in SYSCR in extended mode with on-chip ROM. Otherwise, it should be

noted that an address bus is output to the corresponding pin.

DR data is output when the corresponding pin is used as port output. A value corresponding to

PWM 256/256 output is determined by the OS bit, so the value should have been set to DR

beforehand.

9.3.5

Peripheral Clock Select Register (PCSR)

PCSR selects the PWM input clock.

Bit

Bit Name

Initial Value

R/W

Description

3—

Reserved

This bit is always read as 0. The initial value should not

be changed.

PWCKB

PWCKA

R/W

PWM Clock Select B, A

Together with bits PWCKE and PWCKS in PWSL,

these bits select the internal clock input to TCNT in the

PWM. For details, see table 9.2.

0—

Reserved

This bit is always read as 0. The initial value should not

be changed.

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