HD64F2145 datasheet(227/829 Pages) RENESAS

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Rev. 2.0, 08/02, page 187 of 788

8.10.1

Port 9 Data Direction Register (P9DDR)

P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.

Bit

Bit Name

Initial

Value

R/W

Description

P97DDR

P96DDR

1/0*

P95DDR

P94DDR

P93DDR

P92DDR

P91DDR

P90DDR

P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2

and 3).

Modes 1, 2, and 3 (EXPE = 1):

Pin P97 functions as a bus control input (

:$,7), the IIC_0

I/O pin (SDA0), or an I/O port, according to the wait mode

setting. When P97 functions as an I/O port, it becomes an

output port when P97DDR is set to 1, and an input port

when P97DDR is cleared to 0.

Pin P96 functions as the ø output pin when P96DDR is set

to 1, and as the subclock input (EXCL) or an input port

when P96DDR is cleared to 0.

Pins P95 to P93 automatically become bus control outputs

(

$6/,26, +:5, 5'), regardless of the input/output

direction indicated by P95DDR to P93DDR.

Pins P92 and P91 become output ports when P92DDR

and P91DDR are set to 1, and input ports when P92DDR

and P91DDR are cleared to 0.

When the ABW bit in WSCR is cleared to 0, pin P90

becomes a bus control output (

/:5), regardless of the

input/output direction indicated by P90DDR. When the

ABW bit is 1, pin P90 becomes an output port if P90DDR

is set to 1, and an input port if P90DDR is cleared to 0.

Modes 2 and 3 (EXPE = 0):

When the corresponding P9DDR bits are set to 1, pin P96

functions as the ø output pin and pins P97 and P95 to P90

become output ports. When P9DDR bits are cleared to 0,

the corresponding pins become input ports.

Note:* The initial value of P96DDR is 1 (mode 1) or 0 (modes 2 and 3).

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