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56F802 bảng dữ liệu(PDF) 20 Page - Freescale Semiconductor, Inc |
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56F802 bảng dữ liệu(HTML) 20 Page - Freescale Semiconductor, Inc |
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20 / 40 page ![]() 56F802 Technical Data, Rev. 7 20 Freescale Semiconductor Table 3-6 IFREN Truth Table Mode IFREN = 1 IFREN = 0 Read Read information block Read main memory block Word program Program information block Program main memory block Page erase Erase information block Erase main memory block Mass erase Erase both blocks Erase main memory block Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Figure Program time Tprog* 20 – – us Figure 3-4 Erase time Terase* 20 – – ms Figure 3-5 Mass erase time Tme* 100 – – ms Figure 3-6 Endurance1 1. One Cycle is equal to an erase program and read. ECYC 10,000 20,000 – cycles Data Retention1 @ 5000 cycles DRET 10 30 – years The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time Tnvs* – 5 – us Figure 3-4, Figure 3-5, Figure 3-6 NVSTR hold time Tnvh* – 5 – us Figure 3-4, Figure 3-5 NVSTR hold time (mass erase) Tnvh1* – 100 – us Figure 3-6 NVSTR to program set up time Tpgs* – 10 – us Figure 3-4 Recovery time Trcv* – 1 – us Figure 3-4, Figure 3-5, Figure 3-6 Cumulative program HV period2 Thv – 3 – ms Figure 3-4 Program hold time3 Tpgh – – – Figure 3-4 Address/data set up time3 Tads – – – Figure 3-4 Address/data hold time3 Tadh – – – Figure 3-4 |
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