DAC5687IPZP datasheet(54/72 Pages) TI

tên linh kiện	DAC5687IPZP

Giải thích chi tiết về linh kiện	16-BIT, 500 MSPS 2x-8x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

PDF	72 Pages

Scroll/Zoom	100%

nhà sản xuất	TI [Texas Instruments]

Trang chủ	http://www.ti.com

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200

Ω

CLK

1:4

CLKC

Termination Resistor

Swing Limitation

Optional, May Be Bypassed

for Sine Wave Input

CAC

0.1

µF

S0029-01

Ropt

Ω

CLK

1:1

CLKC

Optional, Reduces

Clock Feedthrough

CAC

0.01

µF

TTL/CMOS

Source

Ropt

Ω

CLK

CLKC

Node CLKC Internally Biased

to CLKVDD 2

TTL/CMOS

Source

0.01

µF

S0030-01

130

Ω

CAC

0.1

µF

CAC

0.1

µF

130

Ω

VTT

Differential

ECL

(LV)PECL

Source

–

CLK

CLKC

82.5

Ω

82.5

Ω

100

Ω

S0031-01

Power Up Sequence

DAC5687

SLWS164B – FEBRUARY 2005 – REVISED JUNE 2005

Figure 62. Preferred Clock Input Configuration

Figure 63. Driving the DAC5687 With a Single-Ended TTL/CMOS Clock Source

Figure 64. Driving the DAC5687 With Differential ECL/PECL Clock Source

In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or

simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order.

Within AVDD, the multiple AVDD pins should be powered simultaneously.

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