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DAC5687IPZP bảng dữ liệu(PDF) 53 Page - Texas Instruments |
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DAC5687IPZP bảng dữ liệu(HTML) 53 Page - Texas Instruments |
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53 / 72 page ![]() www.ti.com Digital Inputs DA[15:0] DB[15:0] SLEEP PHSTR TxENABLE QFLAG SDIO SCLK SDENB Internal Digital In IOVDD IOGND RESETB Internal Digital In IOVDD IOGND Clock Inputs CLK Internal Digital In CLKC CLKGND R1 10 k Ω CLKVDD R1 10 k Ω R2 10 k Ω R2 10 k Ω CLKVDD CLKVDD S0028-01 DAC5687 SLWS164B – FEBRUARY 2005 – REVISED JUNE 2005 Applying the QMC gain of 1446, equivalent to 2½, increases the signal back to unity gain through the FMIX and the QMC blocks. Note that with this termination, the DAC side of the transformer is not 50- Ω terminated and therefore may result in reflections when used with a cable output. Figure 60 shows a schematic of the equivalent CMOS digital inputs of the DAC5687. DA[0..15], DB[0..15], SLEEP, PHSTR, TXENABLE, QFLAG, SDIO, SCLK, and SDENB have pull-down resistors and RESETB has a pull-up resistor internal to the DAC5687. See the specification table for logic thresholds. Figure 60. CMOS/TTL Digital Equivalent Input Figure 61 shows an equivalent circuit for the clock input. Figure 61. Clock Input Equivalent Circuit Figure 62, Figure 63, and Figure 64 show various input configurations for driving the differential clock input (CLK/CLKC). 53 |
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