MT7697DIN datasheet(46/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 46 of 84

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Table 2-18. I2S Pin Description

Signal Name

Signal Description

Direction (Slave Mode)

I2S_MCLK

The base clock of the function.

Output

I2S_BCLK

The bit clock of the interface

Input

I2S_FS (LRCLK)

The left/right word select line

of the interface

Input

I2S_TX

Digital audio output

Output

I2S_RX

Digital audio input

Input

MT7697D supplies the MCLK of 16MHz. The external CODEC generates BCLK and LRCLK from MCLK.

When configured as the I2S slave mode, the I2S interface can support two modes.

Table 2-19. I2S Slave Mode

Slave Mode Bit Width

Input Sample (Uplink) Output Sample

(Downlink)

BCLK

(Input)

FS (Input)

Mode 1

16b

16KHz, mono

512KHz

16KHz

Mode 2

16b

24KHz, mono

768KHz

24KHz

The mono data is transferred across the I2S bus as left channel information.

In all of the modes above, when the input data is mono, the data of interest is transferred across the

I2S bus on the left channel.

The I2S pins are multiplexed with SPI pins.

The signal waveform of I2S is shown below.

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