GD25LB256DFIS datasheet(12/79 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LB256D

QE bit.

The Quad Enable (QE) bit is a non-volatile read only bit which allows Quad operation. The default value of QE bit is

1, and it cannot be changed so that the Quad IO2 and IO3 pins are enabled all the time.

LB2, LB3 bits.

The LB2, LB3 bits are non-volatile One Time Program (OTP) bits in Status Register (S12-S13) that provide the write

protect control and status to the Security Registers. The default state of LB2-LB3 are 0, the security registers are unlocked.

The LB2-LB3 bits can be set to 1 individually using the Write Register instruction. The LB2-LB3 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0

bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.

The default setting is CMP=0.

SUS1, SUS2 bits

The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an

Erase/Program Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Erase/Program Resume (7AH) command, software reset (66H+99H)

command as well as a power-down, power-up cycle.

EN4B bit

The EN4B bit is a volatile Read/Write bit in the status register (S11) that is set to 1 after executing the Enable 4-byte

Mode command, and cleared to 0 (default ) by the Disable 4-byte Mode command as well as a power-down, power-up cycle.

GD25LB256DFIS bảng dữ liệu(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc.