GD25B256DFIS datasheet(10/82 Pages) GIGADEVICE

10 / 82 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

5. DATA PROTECTION

The GD25B256D provides the following data protection methods:

◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will

return to reset by the following situation:

-Power-Up/Software Reset (66H+99H)

-Write Disable (WRDI)

-Write Status Register (WRSR)

-Page Program (PP)

-Quad Page Program (QPP)

-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

◆

Software Protection Mode:

-The Block Protect (BP3, BP2, BP1, and BP0) bits and Top Bottom (TB) bit define the section of the memory array

that can be read but cannot be change.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep

Power-Down Mode command and software reset (66H+99H).

Table 6. GD25B256D Protected area size

Status Register Content

Memory Content

BP3

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

NONE

511

01FF0000h-01FFFFFFh

64KB

Upper 1/512

510 to 511

01FE0000h-01FFFFFFh

128KB

Upper 1/256

508 to 511

01FC0000h-01FFFFFFh

256KB

Upper 1/128

504 to 511

01F80000h-01FFFFFFh

512KB

Upper 1/64

496 to 511

01F00000h-01FFFFFFh

1MB

Upper 1/32

480 to 511

01E00000h-01FFFFFFh

2MB

Upper 1/16

448 to 511

01C00000h-01FFFFFFh

4MB

Upper 1/8

384 to 511

01800000h-01FFFFFFh

8MB

Upper 1/4

256 to 511

01000000h-01FFFFFFh

16MB

Upper 1/2

00000000h-0000FFFFh

64KB

Lower 1/512

0 to 1

00000000h-0001FFFFh

128KB

Lower 1/256

0 to 3

00000000h-0003FFFFh

256KB

Lower 1/128

0 to 7

00000000h-0007FFFFh

512KB

Lower 1/64

0 to 15

00000000h-000FFFFFh

1MB

Lower 1/32

0 to 31

00000000h-001FFFFFh

2MB

Lower 1/16

0 to 63

00000000h-003FFFFFh

4MB

Lower 1/8

0 to 127

00000000h-007FFFFFh

8MB

Lower 1/4

0 to 255

00000000h-00FFFFFFh

16MB

Lower 1/2

ALL

00000000h-01FFFFFFh

32MB

ALL

00000000h-01FFFFFFh

32MB

ALL

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