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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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GD25B256DFIS bảng dữ liệu(PDF) 55 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256DFIS bảng dữ liệu(HTML) 55 Page - GigaDevice Semiconductor (Beijing) Inc. |
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55 / 82 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 55 Write Extended Addr. Register C5 Yes Yes Extended Addr. Register may need to be changed during a suspend to reach a sector needed for read or program. Read 03 Yes Yes All array reads allowed in suspend. 4Read 13 Yes Yes All array reads allowed in suspend. Fast Read 0B Yes Yes All array reads allowed in suspend. 4Fast Read 0C Yes Yes All array reads allowed in suspend. Dual I/O Fast Read BB Yes Yes All array reads allowed in suspend. 4Dual I/O Fast Read BC Yes Yes All array reads allowed in suspend. Dual Output Fast Read 3B Yes Yes All array reads allowed in suspend. 4Dual Output Fast Read 3C Yes Yes All array reads allowed in suspend. Quad I/O Fast Read EB Yes Yes All array reads allowed in suspend. 4Quad I/O Fast Read EC Yes Yes All array reads allowed in suspend. Quad Output Fast Read 6B Yes Yes All array reads allowed in suspend. 4Quad Output Fast Read 6C Yes Yes All array reads allowed in suspend. Page Program 02 Yes Required for array program during erase suspend. 4Page Program 12 Yes Required for array program during erase suspend. Quad Page Program 32 Yes Required for array program during erase suspend. 4Quad Page Program 34 Yes Required for array program during erase suspend. Program/Erase Resume 7A Yes Required to resume from erase/program suspend. Enable Reset 66 Yes Yes Reset allowed anytime. Reset 99 Yes Yes Reset allowed anytime. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared fro m 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. Figure 63 Program/Erase Suspend Sequence Diagram Command 0 1 2 3 4 5 6 7 75H CS# SCLK SI SO High-Z tSUS Accept read command |
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