GD25B256DFIS datasheet(25/82 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

7.9.

Read Data Bytes at Higher Speed (Fast Read 0BH or 4Fast Read 0CH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte

address (A23-A0) and a dummy Byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content,

at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The

first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each

Byte of data is shifted out.

Figure 13 Read Data Bytes at Higher Speed Sequence Diagram (ADS=0)

Note:

1. The dummy clock number is configurable.

Figure 14 Read Data Bytes at Higher Speed Sequence Diagram (ADS=1)

Note:

1. The dummy clock number is configurable.

Command

0BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

Command

0BH

CS#

SCLK

High-Z

9 10

36 37 38 39

31 30 29

32-bit address

MSB

42 43 44 45

46 47

Data Out1

50 51 52 53

54 55

Data Out2

CS#

SCLK

MSB

Dummy Byte

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