SC16C554DB datasheet(28/51 Pages) PHILIPS

28 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

28 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 15:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable. The internal baud rate counter latch and

Enhance Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch enabled.

LCR[6]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

Logic 0 = no TX break condition (normal default condition).

Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting

the remote receiver to a line break condition.

LCR[5]

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity

format. Programs the parity conditions (see Table 16).

Logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a

logical 1 for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a

logical 0 for the transmit and receive data.

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,

LCR[4] selects the even or odd parity format.

Logic 0 = Odd Parity is generated by forcing an odd number of

logic 1s in the transmitted data. The receiver must be programmed

to check the same format (normal default condition).

Logic 1 = Even Parity is generated by forcing an even number of

logic 1s in the transmitted data. The receiver must be programmed

to check the same format.

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

Logic 0 = no parity (normal default condition).

Logic 1 = a parity bit is generated during the transmission, receiver

checks the data and parity for transmission errors.

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction

with the programmed word length (see Table 17).

Logic 0 or cleared = default condition.

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 18).

Logic 0 or cleared = default condition.

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