SC16C554DB datasheet(25/51 Pages) PHILIPS

25 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

25 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C554B/554DB in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the

LSR, either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1:4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1

Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with

a character.

7.3.1.2

Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

there are one or more FIFO locations empty. The receive interrupt is set when the receive

FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll regardless

of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the

FIFO ﬁll level is above the programmed trigger level.

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