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SC16C554DB bảng dữ liệu(PDF) 23 Page - NXP Semiconductors |
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SC16C554DB bảng dữ liệu(HTML) 23 Page - NXP Semiconductors |
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23 / 51 page  9397 750 13133 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 9 February 2005 23 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7. Register descriptions Table 9 details the assigned bit functions for the SC16C554B/554DB internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10. [1] The value shown represents the register’s initialized HEX value; X = not applicable. [2] These registers are accessible only when LCR[7] = 0. [3] The Special Register set is accessible only when LCR[7] is set to a logic 1. Table 9: SC16C554B/554DB internal registers A2 A1 A0 Register Default [1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 General Register set [2] 0 0 0 RHR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 THR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 IER 00 0 0 0 0 modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 FCR 00 RCVR trigger (MSB) RCVR trigger (LSB) reserved reserved DMA mode select XMIT FIFO reset RCVR FIFO reset FIFO enable 0 1 0 ISR 01 FIFOs enabled FIFOs enabled 0 0 INT priority bit 2 INT priority bit 1 INT priority bit 0 INT status 0 1 1 LCR 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 MCR 00 0 0 autoflow control enable loop back OP2, INTx enable OP1 RTS DTR 1 0 1 LSR 60 FIFO data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 MSR X0 CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS 1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Special Register set [3] 0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 |
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