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NM1282KSLAXAL bảng dữ liệu(PDF) 38 Page - Nanya Technology Corporation.

tên linh kiện NM1282KSLAXAL
Giải thích chi tiết về linh kiện  MCP Specification
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NM1282KSLAXAL bảng dữ liệu(HTML) 38 Page - Nanya Technology Corporation.

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Version 1.3
38
Nanya Technology Corp.
06/2018
All Rights Reserved. ©
2Gb SLC NAND + 2Gb LPDDR2
NM1282KSLAXAL
NTC Proprietary
Level: Property
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.



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