NM1282KSLAXAL datasheet(82/120 Pages) NANYA

82 / 120 page

Version 1.3

Nanya Technology Corp.

06/2018

2Gb SLC NAND + 2Gb LPDDR2

NM1282KSLAXAL

NTC Proprietary

Level: Property

Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOL(AC) and VOH(AC) for single ended signals as shown below.

Single-Ended Output Slew Rate Definition

Description

Defined by

Measured

From

Single-ended output slew rate for rising edge

[VOH(AC)

– VOL(AC)] / ΔTRSE

VOL(AC)

VOH(AC)

Single-ended output slew rate for falling edge

[VOH(AC)

– VOL(AC)] / ΔTFSE

VOH(AC)

VOL(AC)

Notes:

Output slew rate is verified by design and characterization, and may not be subject to production testing.

Single-Ended Output Slew Rate

Symbol

Parameter

LPDDR2 1066

Unit

Min

Max

SRQSE

Single-ended output slew rate (output impedance = 40Ω ± 30%)

1.5

3.5

V/ns

SRQSE

Single-ended output slew rate (output impedance = 60Ω ± 30%)

1.0

2.5

V/ns

Output slew-rate-matching ratio (pull-up to pull-down)

0.7

1.4

Definitions:

SR = slew rate, Q = query output (similar to DQ = data-in, query-output), se = single-ended signals

NOTE 1 Measured with output reference load.

NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire

temperature and voltage range. For a given output, it represents the maximum difference between pull-up and

pull-down drivers due to process variation.

NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

NOTE 4 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of

DQ signals per data byte driving logic-low.

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