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PCF8813 bảng dữ liệu(PDF) 52 Page - NXP Semiconductors |
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PCF8813 bảng dữ liệu(HTML) 52 Page - NXP Semiconductors |
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52 / 72 page ![]() 2004 Mar 05 52 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 17.5 Interface commands Instructions additional to those of the instruction set (Table 5) are given in Table 21. Table 21 Additional instructions INSTRUCTION D/CR/W COMMAND BYTE ACTION D7 D6 D5 D4 D3 D2 D1 D0 Reset enable OTP circuitry Function set 0000100000 exit Power-down REF (refresh) 000001000 PC switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect Function set 0000100101 set PD = 1 and H = 1 MM 0000011110 enter MM mode 17.5.1 DISABLE OTP COMMAND This is a special instruction for the PCF8813 which disables all included OTP circuitry. In this case, all OTP-related commands are inactive. VCAL and MF have no effect on VLCD and manufacture identification respectively. Once disabled, the mode can only be enabled via a reset. 17.5.2 MODULE MAKER CALIBRATION Instruction (MM) enters the device into the calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set, then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit D7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C=0 and has only three significant bits, thus the remaining five bits are ignored. Bit D7 is the continuation bit (D7 = 1 indicates remain in MM mode; D7 = 0 indicates exit MM mode). D6 has to be logic 0 until the last bit when the seal bit is set, in which case this is set to logic 1 (D6 is set to logic 1 only when the high voltage used for programming the cells is about to be applied). Bit D0 is the data bit and its value is shifted into the OTP shift register on the falling edge of the SCLK clock. 17.5.3 REFRESH The action of the refresh instruction (REF) is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the PCF8813, the refresh instruction is associated with the power control instruction so that the shift register is refreshed automatically every time the high voltage generator is enabled or disabled. However, if this instruction is sent while in Power-down, the PC bits are updated but the refreshing is ignored. 17.6 Filling the shift register An example of the sequence of commands and data for filling the shift register is shown in Table 22. This example uses the values VCAL = −4 (11100B), MF = 4 (100B is the Philips identifying code) and the seal bit is 0. It is assumed that the PCF8813 has just been reset. After transmitting the last bit the PCF8813 can exit or remain in MM mode (see Table 22, step 1). When in MM mode, the interface does not recognize commands in the normal sense. After this sequence has been applied, it is possible to observe the impact of the data shifted in. The sequence described is not useful for OTP programming because the number of bits with value = 1 is greater than that allowed for programming (see Section 17.7). Figure 49 shows the shift register after this action. |
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