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TUSB8044AI bảng dữ liệu(PDF) 46 Page - Texas Instruments

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TUSB8044AI bảng dữ liệu(HTML) 46 Page - Texas Instruments

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46
TUSB8044A
SLLSF92 – FEBRUARY 2019
www.ti.com
Product Folder Links: TUSB8044A
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
8.5.33 SMBus Device Status and Command Register
Figure 34. Register Offset F8h
Bit No.
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
0
Table 41. Bit Descriptions – SMBus Device Status and Command Register
Bit
Field
Type
Description
7:2
RSVD
RO
Reserved. Read only, returns 0 when read.
1
smbusRst
RSU
SMBus interface reset. This bit loads the registers back to their GRSTz
values. Note, that since this bit can only be set when in SMBus mode
the cfgActive bit is also reset to 1. When software sets this bit it must
reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion
of the reset. A write of 0 has no effect.
0
cfgActive
RCU
Configuration active. This bit indicates that configuration of the
TUSB8044A is currently active. The bit is set by hardware when the
device enters the I2C or SMBus mode. The TUSB8044A shall not
connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the
TUSB8044A exits the I2C mode.
When in the SMBus mode, this bit must be cleared by the SMBus host
in order to exit the configuration mode and allow the upstream port to
connect.
The bit is cleared by a writing 1. A write of 0 has no effect.
8.5.34 Billboard String1_2
Figure 35. Register Offset 100h - 2DFh (Billboard String1_2)
Bit No.
7
6
5
4
3
2
1
0
Reset State
X
X
X
X
X
X
X
X
Table 42. Bit Descriptions – Billboard String1_2
Bit
Field
Type
Description
7:0
BBString12
W
Billboard String1 and String2. This field can only be written to and can
not be read from.
String 1 defaults http://www.displayport.org
String 2 defaults to "DisplayPort"
The default can be changed using an external I2C EEPROM or
SMBus.



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