TUSB8044AI datasheet(45/63 Pages) TI1

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TUSB8044A

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SLLSF92 – FEBRUARY 2019

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8.5.32 Additional Feature Configuration Register

Figure 33. Register Offset F0h

Bit No.

Reset State

Table 40. Bit Descriptions – Additional Feature Configuration Register

Bit

Field

Type

Description

7:5

Reserved

Reserved. This field defaults to 3'b000 and must not be changed.

stsOutputEn

Status output enable. This field when set enables of the Status output

signals, HS_UP, HS_SUSPEND, SS_UP, SS_SUSPEND.

0 = STS outputs are disabled.

1 = STS outputs are enabled.

This bit may be loaded by EEPROM or over-written by a SMBUS host.

3:1

pwronTime

Power On Delay Time. When the efuse_pwronTime field is all 0s, this

field sets the delay time from the removal disable of PWRCTL to the

enable of PWRCTL when transitioning battery charging modes. For

example, when disabling the power on a transition from ACP to DCP

Mode. The nominal timing is defined as follows:

TPWRON_EN = (pwronTime x 1) x 200 ms

(1)

This field may be over-written by EEPROM contents or by an SMBus

host.

usb3spreadDis

USB3 Spread Spectrum Disable. This bit allows firmware to disable the

spread spectrum function of the USB3 phy PLL.

0 = Spread spectrum function is enabled

1= Spread spectrum function is disabled

This bit may be loaded by EEPROM or over-written by a SMBUS host.

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