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[1]

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.

[2]

All ports are in input-only (high-impedance) state after power-up.

[3]

The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4]

The only reset source that affects these SFRs is power-on reset.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on

reset. Other resets will not affect WDTOF.

RSTSRC

Reset source register

DFh

-

-

BOF

POF

-

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1h

RTCF

RTCS1

RTCS0

-

-

-

ERTC

RTCEN

60 [2]

[4]

011xxx00

RTCH

Real-time clock register high

D2h

00 [4]

00000000

RTCL

Real-time clock register low

D3h

00 [4]

00000000

SP

Stack pointer

81h

07

00000111

TAMOD

Timer 0 and 1 auxiliary mode

8Fh

-

-

-

T1M2

-

-

-

T0M2

00

xxx0xxx0

Bit address

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer 0 and 1 control

88h

TF1

TR1

TF0

TR0

----

00

00000000

TH0

Timer 0 high

8Ch

00

00000000

TH1

Timer 1 high

8Dh

00

00000000

TL0

Timer 0 low

8Ah

00

00000000

TL1

Timer 1 low

8Bh

00

00000000

TMOD

Timer 0 and 1 mode

89h

-

-

T1M1

T1M0

-

-

T0M1

T0M0

00

00000000

TRIM

Internal oscillator trim register

96h

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [4]

WDCON

Watchdog control register

A7h

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

[6] [4]

WDL

Watchdog load

C1h

FF

11111111

WFEED1

Watchdog feed 1

C2h

WFEED2

Watchdog feed 2

C3h

Table 7:

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary