P89LPC9103 datasheet(49/58 Pages) PHILIPS

49 / 58 page

9397 750 14655

Product data sheet

Rev. 02 — 11 April 2005

49 of 58

Philips Semiconductors

P89LPC9102/9103/9107

8-bit microcontrollers with two-clock accelerated 80C51 core

12. Dynamic characteristics

[1]

Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

Table 13:

Dynamic characteristics (12 MHz)

VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

Tamb = −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

Variable clock

fext =12MHz

Unit

Min

Max

Min

Max

fOSC(RC)

internal RC oscillator frequency

(nominal f = 7.3728 MHz) trimmed

±1 % at T

amb =25 °C

clock doubler

option = OFF

(default)

7.189

7.557

7.189

7.557

MHz

internal RC oscillator frequency

(nominal f = 14.7456 MHz)

clock doubler

option = ON,

VDD = 2.7 V to

3.6 V

14.378

15.114

14.378

15.114

MHz

fOSC(WD)

internal watchdog oscillator

frequency (nominal f = 400 kHz)

320

520

320

520

kHz

Tcy(CLK)

clock cycle time

see Figure 19

fCLKLP

low power select clock frequency

MHz

External clock

fext

external clock frequency

MHz

tCHCX

HIGH time

VDD = 2.7 V to

3.6 V; see

Figure 19

Tcy(CLK) − tCLCX

tCLCX

LOW time

Tcy(CLK) − tCHCX

tCLCH

rise time

tCHCL

fall time

Glitch ﬁlter

tgr

glitch rejection

P1.5/RST pin

any pin except

P1.5/RST

tsa

signal acceptance

P1.5/RST pin

125

any pin except

P1.5/RST

Shift register (UART mode 0 - P89LPC9103)

tXLXL

serial port clock cycle time

see Figure 18

16Tcy(CLK)

1333

tQVXH

output data set-up to clock rising

edge

see Figure 18

13Tcy(CLK)

1083

tXHQX

output data hold after clock rising

edge

see Figure 18

-Tcy(CLK) + 20

103

tXHDX

input data hold after clock rising

edge

see Figure 18

-0

tXHDV

input data valid to clock rising edge see Figure 18

150

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