SCD1284 datasheet(149/176 Pages) INTEL

149 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

149

Any change in the mode of the parallel port is reported to the peripheral host by interrupt if the

NegCh bit (PCIER[5]) is set; host software then reads the NSR to determine the current status and

condition. Once the host has read the NSR status resulting from the current negotiation, it should

clear the register in preparation for additional negotiation cycles. The NSR can be cleared by

writing any value.

7.8.7

Ones Detect Register

Bit

Description

Negotiation OK: The state of this bit indicates that the negotiation was successful.

Negotiation Failed: The state of this bit indicates that the negotiation failed. The result code indicates which

mode was attempted

Host Timeout: This bit indicates that a host timeout occurred on the parallel channel. The accompanying 4-

bit result code indicates that the link has returned to Compatibility mode (x02). See the description of HTVR in

Section 7.8.2 on page 146.

Immediate Termination: This bit indicates that the A1284 signal has unexpectedly gone inactive as a result

of an immediate termination from the host and the interface and has reentered Compatibility mode. The 4-bit

negotiation result code should indicate which mode was terminated.

3:0

The lower 4 bits of this register contain a result code that shows the current mode. The following table shows

the encoding of the result code.

Compatible mode — no negotiation.

Failed negotiation.

Compatible mode — termination of a 1284 mode.

001

Reserved.

010

011

EPP mode.

Reserved.

Reverse Nibble mode.

Reverse Nibble mode — ID request.

Reverse Byte mode.

Reverse Byte mode — ID request.

ECP mode without RLE.

ECP mode without RLE — ID request.

ECP mode with RLE.

ECP mode with RLE — ID request.

Access: Read/Write

8-Bit Hex Address: 2D

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A1284

nInit

HstBsy

HstClk

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