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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SCD1284 bảng dữ liệu(PDF) 44 Page - Intel Corporation |
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SCD1284 bảng dữ liệu(HTML) 44 Page - Intel Corporation |
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44 / 176 page  CD1284 — IEEE 1284-Compatible Parallel Interface Controller 44 Datasheet • NegCh for negotiation changes • SigCh for signal changes on the port status inputs (Manual mode only) • EPPAW for EPP protocol address writes • DirCh for direction changes on the parallel channel • IDReq for slave ID requests from the remote master. • nINIT for initialization pulses from the master (Compatibility mode only) Any or all of these bits may be set, based on the mode of operation. The NegCh interrupt is issued whenever the remote master performs a protocol change, such as moving from Compatibility mode to ECP; the CPU examines the NSR to determine the new state of the parallel interface. Signal changes can be identified by reading the SSR. In response to the EPPAW interrupt, the CPU would read the EAR to retrieve the value that was written during the EPP address write cycle. |
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