AD9154-EBZ datasheet(98/124 Pages) AD

98 / 124 page

AD9154

Data Sheet

Rev. C | Page 98 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

PD_PCLK

Power-Down Calibration Reference/SERDES PLL Clock.

0x1

R/W

0 Enable clock to SERDES PLL/calibration logic.

1 Disable clock to SERDES PLL/calibration logic.

PDCLOCKREC

Power-Down Clock Receiver.

0x1

R/W

0 Enable clock receiver analog buffer.

1 Power-down clock receiver analog buffer.

DUTY_EN

Enable Duty Cycle Control of Clock Receiver, Always = 1.

0x1

R/W

RF_SYNC_EN

Enable SYSREF± timing for RF clock chain.

0x1

R/W

RF_CLKDIV_EN

Enable RF Clock Divider. The RF clock divider divides

the input clock by 2 and provides the result to the

DAC for sampling.

0x0

R/W

0 RF clock divider disabled.

1 RF clock divider enabled.

0x081

SYSREF_

ACTRL0

[7:5]

RESERVED

Reserved.

0x0

PDSYSREF

Power Down SYSREF± Buffer. This bit powers down

the SYSREF± receiver. For Subclass 1 operation to

work, this buffer must be enabled.

0x1

R/W

HYS_ON

Hysteresis On. This bit enables the programmable

hysteresis control for the SYSREF± receiver.

0x0

R/W

0 Disable hysteresis in SYSREF± receiver.

1 Enable hysteresis in SYSREF± receiver.

SYSREF_RISE

Use SYSREF± Rising Edge.

0x0

R/W

0 Use SYSREF± falling edge for alignment.

1 Use SYSREF± rising edge for alignment.

[1:0]

HYS_CNTRL1

MSBs of Hysteresis Control. Hysteresis control bits are

control bits for the amount of hysteresis in the

SYSREF± receiver. Each of the ten bits adds 10 mV of

differential hysteresis to the receiver input. Two of

the 10 bits are contained here. The other 8 bits are in

HYS_CNTRL0.

0x0

R/W

0x082

SYSREF_

ACTRL1

[7:0]

HYS_CNTRL0

Low Bits of Hysteresis Control. Hysteresis control bits

are control bits for the amount of hysteresis in the

SYSREF± receiver. Each of the ten bits adds 10 mV of

differential hysteresis to the receiver input. Eight of

the 10 bits are contained here. The other 2 bits are in

HYS_CNTRL1.

0x0

R/W

0x083

DACPLLCNTRL

SYNTH_RECAL

Recalibrate VCO Band. Set this bit to reinitialize the

calibration of the VCO band in the DAC PLL. This bit

does not power cycle the DAC PLL, nor does it

recalibrate the charge pump. Set this bit after

changing any setting associated with the PLL. Do not

set this bit until after an initial PLL lock is achieved.

0x0

R/W

[6:5]

RESERVED

Reserved.

0x0

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