LPC47M192 datasheet(91/228 Pages) SMSC

91 / 228 page

SMSC DS – LPC47M192

Page 91

Rev. 03/30/05

DATASHEET

Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.

Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 43 - Mode Descriptions

MODE

DESCRIPTION*

000

SPP mode

001

PS/2 Parallel Port mode

010

Parallel Port Data FIFO mode

011

ECP Parallel Port mode

100

EPP mode (If this option is enabled in the configuration registers)

101

Reserved

110

Test mode

111

Configuration mode

*Refer to ECR Register Description

DATA and ecpAFifo PORT

ADDRESS OFFSET = 00H

Modes 000 and 001 (Data Port)

The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by

RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this

ports are read and output to the host CPU.

Mode 011 (ECP FIFO - Address/RLE)

A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the

ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the

forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing

Diagrams section of this data sheet .

DEVICE STATUS REGISTER (dsr)

ADDRESS OFFSET = 01H

The Status Port is located at an offset of ‘01H’ from the base address. Bits0 - 2 are not implemented as register bits,

during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as

follows:

BIT 3 nFault

The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.

BIT 4 Select

The level on the Select input is read by the CPU as bit 4 of the Device Status Register.

BIT 5 PError

The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register.

BIT 6 nAck

The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.

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