LPC47M192 datasheet(34/228 Pages) SMSC

34 / 228 page

SMSC DS – LPC47M192

Page 34

Rev. 03/30/05

DATASHEET

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the

DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be

written to at any time.

MOT

EN3

MOT

EN2

MOT

EN1

MOT

EN0

DMAEN

nRESET

DRIVE

SEL1

DRIVE

SEL0

RESET

COND.

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to

this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR

BIT 3 DMAEN

PC/AT and Model 30 Mode:

Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA

and interrupt functions. This bit is a logic “0” after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared

to a logic “0”.

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.

DRIVE

DOR VALUE

1CH

2DH

Table 3 – Internal 2 Drive Decode – Normal

DIGITAL OUTPUT

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 5

Bit 4

Bit1

Bit 0

nDS1

nDS0

nMTR1

nMTR0

nBIT 5

nBIT 4

nBIT 5

nBIT 4

nBIT 5

nBIT 4

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