GMS77C1001 datasheet(40/44 Pages) HYNIX

40 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

16. Power-Down Mode (SLEEP)

For applications where power consumption is a critical

factor, device provides power down mode with Watchdog

operation. Executing of SLEEP Instruction is entrance to

SLEEP mode. In the SLEEP mode, oscillator is turn off

and system clock is disable and all functions is stop, but all

registers and RAM data is held. The wake-up sources from

SLEEP mode are external RESET pin reset and watchdog

time-overflow reset.

16.1 SLEEP

The Power-Down mode is entered by executing a SLEEP

instruction. If enabled, the Watchdog Timer will be cleared

but keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had be-

fore the SLEEP instruction was executed (driving high,

driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT time-

out does not drive the RESET pin low.

For lowest current consumption while powered down, the

EC0 input should be at VDD or VSS and the RESET pin

must be at a logic high level .

FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET

FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET

Oscillator

(XIN pin)

Internal

System Clock

Internal

RESET

Fetch SLEEP

Execute SLEEP

Fetch RESET vector

Instruction

TIRT

Oscillator

(XIN pin)

Internal

System Clock

Internal

RESET

WDT

Fetch SLEEP

Execute SLEEP

Fetch RESET vector

Instruction

TIRT

Overflow

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