GMS77C1001 datasheet(23/44 Pages) HYNIX

23 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

9.3.2 TMR0 Register

The TMR0 register is a data register for 8-bit timer/

counter. In reset state, the TMR0 register is initialized with

“00H”.

9.3.3 Program Counter (PC)

The program counter contains the 10-bit address of the in-

struction to be executed(9-bit address for GMS77C1000).

The lower 8 bits of the program counter are contained in

the PCL register which can be provided by the instruction

word for a call instruction, or any instruction where the

PCL is the destination while the ninth bit of the program

counter comes from the page address bit - PA0 of the STA-

TUS register(GMS77C1001 only).

This is necessary to cause program branches across pro-

gram memory page boundaries.

Prior to the execution of a branch operation, the user must

initialize the PA0 bit of STATUS register.

The eighth bit of the program counter can come from the

instruction word by execution of goto instruction, or can be

cleared by execution of call or any instruction where the

PCL is the destination.

In reset state, the program counter is initialized with

“1FFH”(GMS77C1000) or “3FFH”(GMS77C1001).

Note: Because PC<8> is cleared in the subroutine call in-

struction, or any Modify PCL instruction, all subrou-

tine calls or computed jumps are limited to the first

256 locations of any program memory page (512

words long).

9.3.4 Stack Operation

The GMS77C1000/1001 have a 2-level hardware stack.

The stack register consists of two 9-bit save regis-

ters(GMS77C1000), 10-bit save registers(GMS77C1001).

A physical transfer of register contents from the program

counter to the stack or vice versa, and within the stack, oc-

curs on call and return instructions. If more than two se-

quential call instructions are executed, only the most recent

two return address are stored. If more than two sequential

return instructions are executed, the stack will be filled

with the address previously stored in level 2. The stack

cannot be read or written by program.

jump instrunciton

subroutine call instruction

FIGURE 9-5 LOADING OF BRANCH INSTRUCTION -

GMS77C1000

PCL

Instruction Word

PCL

Instruction Word

Reset to ‘0’

jump instruction

subroutine call Instruction

FIGURE 9-6 LOADING OF BRANCH INSTRUCTION -

GMS77C1001

FIGURE 9-7 OPERATION OF 2-LEVEL STACK

PCL

Instruction Word

PA0

PCL

Instruction Word

PA0

Reset to ‘0’

STACK LEVEL1

STACK LEVEL2

9(8)

return

subroutine call

GMS77C1001(GMS77C1000)

subroutine call

GMS77C1001 bảng dữ liệu(PDF) 23 Page - Hynix Semiconductor

GMS77C1001 bảng dữ liệu(HTML) 23 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

bảng dữ liệu tải về

Link URL