P89LPC915FDH datasheet(44/72 Pages) PHILIPS

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Philips Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 04 — 17 December 2004

44 of 72

9397 750 14397

9.18.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is

stored in RB8 in Special Function Register SCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 9.18.5 “Baud rate generator and selection”).

9.18.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0),

8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When

data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of

logic 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8.

When data is received, the 9th data bit goes into RB8 in Special Function Register

SCON, while the stop bit is not saved. The baud rate is programmable to either 1

⁄16 or

⁄

32 of the CCLK frequency, as determined by the SMOD1 bit in PCON.

9.18.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). In fact,

Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in

Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate

Generator (described in section Section 9.18.5 “Baud rate generator and selection”).

9.18.5

Baud rate generator and selection

The P89LPC915/916/917 has an independent Baud Rate Generator. The baud rate

is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs

which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing

functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 13).

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses CCLK.

9.18.6

Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is logic 1, framing errors can be made available in SCON.7, respectively. If

SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1

(SCON.7:6) are set up when SMOD0 is logic 0.

Fig 13. Baud rate sources for UART (Modes 1, 3).

Baud Rate Modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

¸2

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

002aaa419

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