T7906EKTSLASHSC datasheet(5/42 Pages) ATMEL

5 / 42 page

T7906E

Rev. A – 27-Aug.-01

Block Diagram

Memory Interface

The RAM interface provides a 16-bit data bus and 16-bit address bus. Four chip select

lines allow to address four different memory partitions (banks). This partitioning into dif-

ferent banks is done using 4 internal address boundary registers. These are 8 bit wide

and provide a minimum page size of 1024 words. The memory interface can be pro-

grammed to use 0 to 7 wait states.

GPIO Interface

The general purpose I/O (GPIO Interface) provides up to 24 bidirectional signal lines.

The direction (input or output) of each GPIO line can be set individually via register.

Data to/from the GPIO lines is written/read via the GPIO data register. The GPIO pro-

vides 8 dedicated I/O lines, the remaining 16 lines of the port are shared with the ADC

address and host data bus. These GPIO lines are available when the corresponding unit

(e.g. the host data bus) of the T7906Eis not being used (disabled).

UART interface

Two independent UARTs are included in the T7906E as well. One UART uses dedi-

cated I/O lines whereas the second UART is sharing its pins with the GPIO port. The

transmit rate of the UARTs in bps can be programmed via a 12-bit wide register with a

maximum bit rate of about 780 kbit/s. The UARTs can optionally use hardware hand-

shake (rts/cts).

Host Interface

Although the T7906E is primarily designed to be remotely controlled, it can nevertheless

be programmed and controlled by a local host if required. For that purpose a host inter-

face provides 8 multiplexed data and address lines.

Timers / Event Counter

Two 32-bit on-chip timers are available on the T7906E. Each timer provides a 32 bit

counter and a 32 bit reload register. The two timers can be operated independently or

JTAG

UART

GPIO

Link

Interface

Host

Interface

system

util.

system

util.

Internal

Controller

Timer

ADC

I/F

ADC

I/F

ADC

I/F

ADC

I/F

DAC

I/F

RAM

I/F

FIFO

I/F

Internal

bus

control

& data control

address/command

bus

Internal control

data bus

transmit/receive

data bus

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