T7906EKTSLASHSC datasheet(7/42 Pages) ATMEL

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T7906E

Rev. A – 27-Aug.-01

Programming the T7906E

Programming the T7906E internal registers is done via a simple protocol over the IEEE-

1355 link or directly via the host interface. The link protocol consists of a command byte

and, if necessary, one or more data bytes.

All internal registers are 8-bit wide addressable. Two commands (read and write) suffice

to access all registers of the T7906E.

The T7906E provides registers and ports; a register contains exactly one byte (read /

write), whereas a port (e.g. a FIFO interface) behaves like a FIFO, meaning that multiple

data bytes can be read or written from/to the port.

The ports of the T7906E such as the FIFO, UART, ADC and RAM interface are

accessed by a read/write command to the corresponding port address. In the case of

FIFO, Host, UART and memory interface, a packet oriented access is also possible

(meaning transferring multiple data bytes with a single command).

The read/write selection of a command is done by setting bit7 (msb) of the first byte to

one (read) or zero (write).

Signal Description

This section describes the signals of the T7906E. Groups of signals represent busses

where the highest number is the MSB.

Signal

Direction

Description

max. output load

Signal

[mA]

[pF]

HSEL*

when low, the external host selects the T7906E host

interface

HWRnRD

host interface write/read signal

if HWRnRD is high during HSEL* low, the host writes

data to the address register or to the T7906E

registers.

if HWRnRD is low during HSEL* low, the host reads

data from the address register or the T7906E

registers.

HDATnADR

host interface data/address signal

if HDATnADR is high during read, the host

reads/writes data from/to the internal T7906E

(data) registers.

if HDATnADR is low during read, the host

reads/writes address from/to the address register.

HDATA(7:0)

I/O

T7906E data bus.

This data lines will be used to access

the T7906E registers.

HDATA(7:0) can also be used as GPIO(2), if

Host interface is disabled.

350

HINTR*

host interrupt request line

TMR1_CLK

timer1 clock (max. 12.5 MHz)

TMR1_EXP

timer1 expired. Asserted for one cycle

if the value of counter1 is equal to the

content of register TPERIOD1(3:0).

350

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