T7906EKTSLASHSC datasheet(8/42 Pages) ATMEL

8 / 42 page

T7906E

Rev. A – 27-Aug.-01

Note:

1. IOB15-0, IOB21-18: 6 mA

IOB17-16: 8mA

IOB24-22: 3mA

IOB27-25: input only

All inputs have an internal pull-up resistor, with the following exceptions, which have an

internal pull-down resistor: LDI, LSI, TRST*, TMS.

TMR2_CLK

timer2 clock (max. 12.5 MHz)

TMR2_EXP.

timer2 expired. Asserted for one cycle

if the value of counter2 is equal to the

content of register TPERIOD2(3:0)

RxD1

receive data to UART1

TxD1

transmit data from UART1

LDI

Link Data Input

LSI

Link Strobe Input

LDO

Link Data Output

LSO

Link Strobe Output

DATA(15:0)

I/O

common T7906E data bus

GPIO(7:0)

I/O

General purpose input/output lines.

IOB(27:0)

I/O

Control bus. The T7906E controls the connected

interface via these lines. The function of each control

signal is described in a separate table.

see note (1)

TRST*

Test Reset. Resets the test state machine.

TCK

Test Clock. Provides an asynchronous clock for JTAG

boundary scan

TMS

Test Mode Select. Used to control the test state

machine. This input should be left unconnected or tied

to ground during normal operation!

TDI

Test Data Input. Provides serial data for the boundary

scan logic

TDO

O/Z

Test Data Output. Serial scan output of the boundary

scan path

350

RESET*

T7906E Reset. Sets the T7906E to a known state.

This input must be asserted (low) at power-up. The

minimum width of RESET low is 2 cycles when CLK is

running

CLK

External clock input to T7906E (max. 5 MHz)

PLLOUT

Output of internal PLL. Used to connect a network of

external RC devices

VCC

Power Supply

GND

Ground

Signal

Direction

Description

max. output load

Signal

[mA]

[pF]

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