MPC755 datasheet(36/56 Pages) MOTOROLA

36 / 56 page

MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

System Design Information

7.6 Mechanical Dimensions for the MPC755

Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC755, 360 PBGA

package.

Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755,

360 PBGA Package

8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC755.

8.1 PLL Configuration

The MPC755 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. These must be chosen such that they

comply with Table 8. Table 16 shows the valid configurations of these signals and an example illustrating the core

and VCO frequencies resulting from various PLL configurations and example bus frequencies. In this example,

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. TOP SIDE A1 CORNER INDEX IS A METALIZED

FEATURE WITH VARIOUS SHAPES. BOTTOM

SIDE A1 CORNER IS DESIGNATED WITH A BALL

MISSING FROM THE ARRAY.

0.2

360X

A1 CORNER

0.2

123456789 10 11 12 13 14 15 16

0.3

0.15

0.2 C

17 18 19

Millimeters

DIM

Min

Max

2.22

2.77

0.50

0.70

1.00

1.20

—

0.60

0.90

25.00 BSC

6.75

25.00 BSC

7.87

1.27 BSC

MPC755 bảng dữ liệu(PDF) 36 Page - Motorola, Inc

MPC755 bảng dữ liệu(HTML) 36 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL