LTC2972 datasheet(63/112 Pages) LINER

63 / 112 page

LTC2972

2972fa

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FAULT RESPONSES

COMMAND NAME

CMD

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS EEPROM

DEFAULT

VALUE

REF

PAGE

VOUT_OV_FAULT_RESPONSE

0x41

Action to be taken by the device when an

output overvoltage fault is detected.

R/W Byte

Reg

0x80

VOUT_UV_FAULT_RESPONSE

0x45

Action to be taken by the device when an

output undervoltage fault is detected.

R/W Byte

Reg

0x7F

OT_FAULT_RESPONSE

0x50

Action to be taken by the device when an

overtemperature fault is detected on the

external temperature sensor.

R/W Byte

Reg

0xB8

<OV>

UT_FAULT_RESPONSE

0x54

Action to be taken by the device when an

undertemperature fault is detected on the

external temperature sensor.

R/W Byte

Reg

0xB8

<OV>

VIN_OV_FAULT_RESPONSE

0x56

Action to be taken by the device when an

input overvoltage fault is detected.

R/W Byte

Reg

0x80

<OV>

VIN_UV_FAULT_RESPONSE

0x5A Action to be taken by the device when an

input undervoltage fault is detected.

R/W Byte

Reg

0x00

<OV>

TON_MAX_FAULT_RESPONSE

0x63

Action to be taken by the device when a

TON_MAX_FAULT event is detected.

R/W Byte

Reg

0xB8

MFR_RETRY_DELAY

0xDB Retry interval during FAULT retry mode.

R/W Word

L11

200

0xF320

MFR_RETRY_COUNT

0xF7

Retry count for all faulted off conditions

that enable retry.

R/W Byte

Reg

0x00

Watchdog Operation

A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the

WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output

is optionally de-asserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the

MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.

MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T

The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval

following assertion of the PWRGD pin, assuming the PWRGD pin reflects the status of the watchdog timer. If assertion

of PWRGD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first

timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables

the watchdog timer. This delay is internally limited to 65 seconds and rounded to the nearest 1ms.

The MFR_WATCHDOG_T register allows the user to program watchdog timer intervals subsequent to the MFR_

WATCHDOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog

timer. This delay is internally limited to 655ms and rounded to the nearest 10µs.

Both timers operate on an internal clock independent of SHARE_CLK. The read value of both commands always returns

what was last written and does not reflect internal limiting.

PMBus COMMAND DESCRIPTION

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