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LTC2972

2972fa

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MFR_RESTART_DELAY

This command essentially sets the off time of a CONTROL pin initiated restart. If the CONTROL pin is toggled off for at

least 10µs then on, all dependent channels are disabled, held off for a time = Mfr_restart_delay, then sequenced back

on. CONTROL pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value

of all zeros disables this feature. This delay is counted using SHARE_CLK only.

This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value of this command

always returns what was last written and does not reflect internal limiting.

Clock Sharing

Multiple ADI PMBus devices can synchronize their clocks in an application by connecting together the open-drain

SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and syn-

chronize all other chips to its falling edge.

SHARE_CLK can optionally be used to synchronize ON/OFF dependency on VIN across multiple chips by setting the

Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_ALL register. When configured this way the chip will hold

SHARE_CLK low when the unit is off for insufficient input voltage, and upon detecting that SHARE_CLK is held low

the chip will disable both channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip

will respond by beginning a start sequence. In this case the slowest VIN_ON detection will take over and synchronize

other chips to its start sequence.

WATCHDOG TIMER AND POWER GOOD

COMMAND NAME

CMD

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS EEPROM

DEFAULT

VALUE

REF

PAGE

MFR_PWRGD_EN

0xD4 Configuration that maps WDI/

RESETB status and individual channel

power good to the PWRGD pin.

R/W Word

Reg

0x0000

MFR_POWERGOOD_ASSERTION_

DELAY

0xE1 Power-good output assertion delay.

R/W Word

L11

100

0xEB20

MFR_WATCHDOG_T_FIRST

0xE2 First watchdog timer interval.

R/W Word

L11

0x8000

MFR_WATCHDOG_T

0xE3 Watchdog timer interval.

R/W Word

L11

0x8000

MFR_PG_CONFIG

0xCB PG pin configuration

R/W Word

Reg

0xC046

MFR_PG_GPO

0xCE PG pin output data register

R/W Byte

Reg

0x00

PMBus COMMAND DESCRIPTION

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