MB91F467BA datasheet(104/127 Pages) CYPRESS

104 / 127 page

MB91460B Series

Document Number: 002-04608 Rev. *A

Page 103 of 126

Power supply

current

F467BA

F466BA

ICC

VDD5R

CLKB: 96 MHz

CLKP: 48 MHz

CLKT: 48 MHz

CLKCAN: 48 MHz



120

150

Code fetch from

Flash

ICCH

VDD5R

TA   25 C



150

A

At stop mode [5]

TA   105 C



0.4

2.0

TA   125 C



1.0

5.0

TA   25 C



100

500

A

RTC: 4 MHz mode [5]

TA   105 C



0.5

2.4

TA   125 C



1.1

5.4

TA   25 C



250

A

RTC: 100 kHz mode

[5]

TA   105 C



0.45

2.2

TA   125 C



1.05

5.2

ILVE

VDD5



150

A

External low voltage

detection

ILVI

VDD5R



100

A

Internal low voltage

detection

IOSC

VDD5



250

500

A

Main clock (4 MHz)



A

Sub clock (32 kHz)

Power supply

current

F465BB

F464BB

ICC

VDD5R

CLKB: 100 MHz

CLKP: 50 MHz

CLKT: 50 MHz

CLKCAN: 50 MHz

110

140

Code fetch from

Flash

ICCH

VDD5R

TA   25 C

150

A

At stop mode [5]

TA   105 C-

0.3

2.0

TA   125 C

0.75

5.0

TA   25 C

100

500

A

RTC: 4 MHz mode [5]

TA   105 C-

0.5

2.4

TA   125 C

0.85

5.4

TA   25 C

250

A

RTC: 100 kHz

mode[5]

TA   105 C-

0.4

2.2

TA   125 C-

0.8

5.2

ILVE

VDD5



150

A

External low voltage

detection

ILVI

VDD5R



100

A

Internal low voltage

detection

IOSC

VDD5

250

500

A

Main clock (4 MHz)

A

Sub clock (32 kHz)

Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.

2. ANn includes all pins where AN channels are enabled.

3. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.

4. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.

5. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.

Parameter

Symbol

name

Condition

Value

Unit

Remarks

Min

Typ

Max

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