PIC18F4539-ESLASHMLSQTP datasheet(308/322 Pages) MICROCHIP

308 / 322 page

PIC18FXX39

DS30485A-page 306

Preliminary

 2002 Microchip Technology Inc.

APPENDIX C: CONVERSION

CONSIDERATIONS

The considerations for converting applications from

previous versions of PIC18 microcontrollers (i.e.,

PIC18FXX2 devices) are listed in Table C-1.

A specific list of resources that are unavailable to

PIC18FXX2 applications in PIC18FXX39 devices is

presented in Table C-2.

TABLE C-1:

CONVERSION CONSIDERATIONS BETWEEN PIC18FXX2 AND PIC18FXX39 DEVICES

TABLE C-2:

UNAVAILABLE RESOURCES (COMPARED TO PIC18FXX2)

Characteristic

PIC18FXX2

PIC18FXX39

Pins

28/40/44

Available Packages

DIP, PDIP, SOIC, PLCC, QFN, TQFP

DIP, PDIP, SOIC, QFN, TQFP

Voltage Range

2.0 - 5.5V

Frequency Range

DC - 40 MHz

4 - 40 MHz (20 MHz optimal)

Available Program Memory (bytes)

16K or 32K

12K or 24K

Available Data RAM (bytes)

768 or 1536

640 or 1408

Data EEPROM

256

Interrupt Sources

17 or 18

15 or 16

Interrupt Priority Levels

Two levels:

low priority (vector at 0008h)

high priority (vector at 0018h)

One level when using Motor Control:

vector at 0008h

Timers (available to users)

Timer1 Oscillator option

yes

Oscillator Switching

yes

Capture/Compare/PWM

2 CCP

2 PWM only, available only through

Motor Control kernel

Motor Control Kernel

yes

A/D

10-bit, 5 or 8 channels,

7 conversion clock selects

10-bit, 5 or 8 channels,

7 conversion clock selects

Communications

PSP, AUSART, MSSP (SPI and I2C)

Code Protection

By 8K block with separate 512-byte

boot block; protection from external

reads and writes, Table Read and

intra-block Table Read

By 8K block with separate 512-byte

boot block; protection from external

reads and writes, Table Read and intra-

block Table Read; Block 3 not protected

on PIC18FX539

Resource Type

Item(s)

I/O Resources

RC1; RC2; T1OSO; T1OSI

Registers

CCP1CON; CCP2CON; CCPR1L; CCPR2L; TMR2; PR2; T2CON; OSCCON

SFR bits

CCP1IE; CCP1IF; CCP1IP; CCP21E; CCP21F; CCP2IP; T1OSCEN; T3CCP1; TMR2ON;

TOUTPS<3:0>; T2CKPS<1:0>; T3CCP2; SFS; RC1; RC2; TRISC1; TRISC2; LATC1; LATC2

Interrupts and

Interrupt Resources

CCP1 Capture/Compare match; CCP2 Capture/Compare match; High priority interrupts

(when Motor Control is used; reserved for Timer2)

Timer Resources

Timer2 (available only through the Motor Control kernel); Timer2 as a clock source for

MSSP module (SPI mode)

CCP Resources

Capture and Compare functionality; Timer1 reset on special event; Timer3 reset on special

event; A/D conversion on special event; Interrupt on special event

Configuration Word bits

OSCEN; CCP2MX; CP3; WRT3; EBTR3

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