INA231AIYFDR datasheet(23/44 Pages) TI1

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INA231

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SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017

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8.6.1 Configuration Register (00h, Read/Write)

Table 4. Configuration Register (00h, Read/Write) Descriptions

BIT #

D15

D14

D13

D12

D11

D10

BIT

NAME

RST

—

AVG2

AVG1

AVG0

VBUSCT2 VBUSCT1 VBUSCT0

VSHCT2

VSHCT1

VSHCT0

MODE3

MODE2

MODE1

POR

VALUE

The Configuration register settings control the operating modes for the INA231. This register controls the

conversion time settings for both the shunt and bus voltage measurements, as well as the averaging mode used.

The operating mode that controls which signals are selected to be measured is also programmed in the

Configuration register.

The Configuration register can be read from at any time without impacting or affecting the device settings or a

conversion in progress. Writing to the Configuration register halts any conversion in progress until the write

sequence is complete, resulting in the start of a new conversion based on the new contents of the Configuration

RST:

Reset Bit

Bit 15

Setting this bit to 1 generates a system reset that is the same as a power-on reset; all registers are reset to default

values. This bit self-clears.

AVG:

Averaging Mode

Bits 9–11

These bits set the number of samples that are collected and averaged together. Table 5 summarizes the AVG bit

settings and related number of averages for each bit.

(1)

Shaded values are default.

8.6.1.1 AVG Bit Settings [11:9]

Table 5. AVG Bit Settings [11:9](1) Description

AVG2

(D11)

AVG1

(D10)

AVG0

(D9)

NUMBER OF

AVERAGES

128

256

512

1024

VBUS CT:

Bus Voltage Conversion Time

Bits 6–8

These bits set the conversion time for the bus voltage measurement. Table 6 shows the VBUS CT bit options and

related conversion times for each bit.

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