L9680 datasheet(53/277 Pages) STMICROELECTRONICS

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L9680

SPI interfaces

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than 32 clocks, the received message is discarded and a SPI_FLT bit is flagged in the

Global Status Word (GSW). The SPI_FLT bit is also set in case of parity error detected on

the MOSI_X frame. Any attempt to access to a register with forbidden access mode (read or

write) is not leading to changes to the internal registers but the SPI_FLT bit is not set in this

case.

7.2

Global SPI register map

The Global SPI interface consists of several 32-bit registers to allow for configuration,

control and status of the IC as well as special manufacturing test modes. The register

definition is defined by the read register ID (RID) and the write register ID (WID) as shown in

Table 6. Global ID bit (GID) is used to extend available register addresses, but it is shared

between RID and WID; only RID and WID with the same GID value can be addressed within

the same SPI word. The operating states here show in which states the SPI command is

processed.

The L9680 checks the validity of the received WID and RID fields in the MOSI_G frame.

Should a SPI write command with WID matching a writable register be received in an illegal

operating state, the command will be discarded and the ERR_WID bit will be flagged in the

next Global Status Word GSW. The ERR_WID flag is not set in case WID is addressing a

read/only register. Should a SPI read command be received containing an unused RID

address, the command will be discarded and the ERR_RID bit will be flagged in the current

GSW.

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