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APPLICATION INFORMATION

APPLICATION EXAMPLE

Z = 50

Ω

Z = 50

Ω

CDCV304

Clock Buffer

25 MHz

P0

P1

VDDO

GNDO

CLKOUT

NC

CLKOUTB

GNDO

VDDO

MULT0

MULT1

P2

VDDREF

REFCLK

VDDP

GNDP

GND

LEADLAG

DLYCTRL

GNDPA

VDDPA

VDDPD

STOPB

PWRDNB

3.3 V

3.3 V

CLK

35

Ω

3.3 V

3.3 V

CDCF5801

CDCV304

Clock Buffer

CLK

Z = 50

Ω; Length = L1

25 MHz

25 MHz

25 MHz

Outputs are Phase Aligned

Between the Two Buffers

3.3 V

Z = 50

Ω; Length = L1

30

Ω

SELECTING VDDREF

CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

The following figure shows an example of using the CDCF5801 as a

×4 multiplier with the phase aligner

de-skewing the unknown buffer delay of the two CDCV304s in the circuit. This circuitry would not be possible

with a simple PLL because the feedback of the PLL would have the second CDCV304 in the loop, causing

instability of the PLL due to a long delay.

Figure 9. Application Example

NOTE:

If an active element (microcontroller, ASIC, DSP< FPYA, DSP, etc.) is used in the

CDCF5801 CLKOUT to DLYCTRL feedback loop, see application report SCAA075.

Generally, VDDREF can be set to any value between 1.2 V and VDD. The setting of VDDREF directly influences

the trigger voltage of the input. Special care must be taken when using small signal swings to drive the

CVDCF5801 input (e.g., PECL). It is recommended to connect VDDREF directly to VDD, ac-couple the REFCLK

input, and rebias the signal.

The following circuit is recommended to drive the CDCF5801 from a differential clock signal like PECL.

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